1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with an improved contact plug suitable for highly integrated semiconductor devices.
2. Description of the Related Art
As is well known, it is essential to reduce the contact resistance in a circuit line width to below 0.16 μm.
According to a recent method of forming a silicon contact plug, a contact hole is first formed and then, polycrystalline silicon is deposited therein. This method is performed by using a Chemical Mechanical Polishing (CMP) process.
Generally, it is desirable to apply selective epitaxial growth (SEG) during the manufacturing process of semiconductor devices since it is possible to reduce cell size, simplify manufacturing processes and improve electrical properties by using SEG.
Therefore, a plug using SEG can solve the problems of gap-fill and of undesirable increase of contact resistance.
Furthermore, it is possible to simplify the manufacturing process by using SEG since it does not require performing CMP and silicon recess etching for plug isolation.
However, there are several problems in applying SEG during plug manufacture.
First, there is a problem with the selectivity of the pattern material, that is, a material to form a window for growing the SEG.
Also, the surface of the nitride layer is exposed when the self-aligned contact (SAC) etch is applied to cell activation regions. The SEG has a different facet generation depending on the selectivity and the thermal stress of the pattern material.
Generally, in a low pressure chemical vapor deposition (LPCVD) process, the nitride materials have difficulty in achieving selectivity at a temperature below 850° C., as compared with oxide materials.
Therefore, the growth speed is lowered in order to have selectivity, thereby increasing the thermal budget on device.
The conventional method for manufacturing a semiconductor device will be described in more detail with reference to accompanying drawings.
FIGS. 1 to 4 are cross sectional views showing the steps of a conventional method of manufacturing semiconductor device.
Referring to FIG. 1, a gate electrode structure 3, having a hard mask (not shown) made of a nitride layer, is formed on a silicon substrate 1 and then, a sidewall spacer 5 is formed on the side of the gate electrode 3.
Although it is not shown in the drawings, impurity junction regions (not shown) are formed by impurities implanted in the silicon substrate 1 on the lower part of both sides of the sidewall spacer 5.
Subsequently, an interlayer insulating layer 7 is deposited by using an oxide layer material on the silicon substrate 1, including the gate electrode structure 3 and the sidewall spacer 5, in order to prevent the generation of short-circuits between adjacent cells.
Referring to FIG. 2, the interlayer insulating layer 7 is subjected to a landing plug contact mask formation process using a photolithography and patterning process to form a landing plug contact hole 9, which exposes the impurity junction regions (not shown), that is, a plug formation area.
Referring to FIG. 3, a polycrystalline silicon layer 11 is then deposited to fill the landing plug contact hole 9 on the upper part of the interlayer insulating layer 7, including the landing plug contact hole 9.
Referring to FIG. 4, a CMP or etch back process is performed on the polycrystalline silicon layer 11, thereby forming a contact plug 11a in the contact hole 9 to be in electrical contact with the impurity junction regions (not shown).
However, the conventional method has several problems in forming a contact hole and a contact plug having a high aspect ratio, wherein the circuit line width is below 0.16 μm.
In particular, one problem in the conventional contact formation process is to have a sufficient plug formation area by using a landing plug contact mask. That is, in the etching process to form a landing plug contact through SAC by a nitride layer spacer of the nitride layer barrier, the problem is that it is difficult to have a sufficient landing plug contact hole area due to the etching grade necessarily generated to have the etching selectivity ratio between the nitride layer of the gate spacer and the oxide layer of the interlayer insulating layer.
In order to solve the problem, SAC of selective single crystal silicon has been proposed as shown in FIG. 5.
FIG. 5 is a cross sectional view for showing the steps of a method of manufacturing a semiconductor device according to another embodiment of the conventional method.
Referring to FIG. 5, an isolation layer 23 is formed to define the device formation region on a silicon substrate 21 and a gate oxide layer 25. A gate 27 and a hard mask 29 are stacked on the device formation region of the silicon substrate 21, thereby obtaining a gate structure. Then, an insulating layer spacer 31 is formed on the upper part and side of the gate structure and at the same time, the silicon substrate 21 is exposed.
Then, a selective episilicon layer is grown over the height of the gate on the surface of the exposed silicon substrate 21, thereby forming a contact plug 33.
Afterwards, an interlayer insulating layer (not shown) is formed to electrically insulate the contact plug and then, additional processes (not shown) are performed.
However, this embodiment of the conventional method has several problems.
First, the allowable margin of the side is very low in the-episilicon growth process.
Therefore, as the device is formed having fine features, the distance between adjacent activation regions becomes shorter. The adhering episilicon layers thereby grow to the side from the adjacent activation regions.
In order to solve this problem, a method has been proposed whereby the episilicon layer is grown by using processes without side growth.
However, there are also several problems in applying the process without side growth.
When the episilicon is applied without side growth, the silicon of the activation region is formed in the shape of a “T” in order to form the contact plug, as shown in FIG. 6, part “A”. According to this method, the side growth of episilicon is actively generated in a curved line. That is, the episilicon is generated in a direction other than in the directions 100 and 110.
FIGS. 7 and 8 are SEM photographs showing cells of direction 100 and cells slanting by 30°, respectively.
Compared with FIG. 7, the episilicon layer of FIG. 8 has the longer distance between activation regions. Therefore, side growth is actively generated and short-circuits may be caused between the adjacent activation regions.
However, it is very difficult to form activation regions in the shape of a “T” since the distance between the adjacent activation regions becomes shorter by the protruding part of the “T” and it is also difficult to form the cell in the shape of a “T” by using a photolithography process.
Furthermore, it is also difficult to obtain episilicon growth in a curved line.
In order to solve the above problems, a method is proposed whereby a contact is formed by a protruding part of a bit line. However, this is also very difficult to successfully perform.